The present invention relates to apparatus and methods for processing chrominance signals of a composite video signal, and, more particularly, to apparatus and methods which incorporate automatic phase control (APC) and automatic chroma control (ACC) operations in processing chrominance signals.
A composite video signal includes a modulated color sub-carrier signal (chrominance signal), shown in FIG. 1A, combined with a monochrome signal (luminance signal) and shown in FIG. 1B. The chrominance signal contains information regarding the color portion of an image, and this information is represented by both the amplitude and phase of the chrominance signal. Because color information is stored in the phase of the signal, an operation that processes the chrominance signal must be closely synchronized with the phase of the signal to avoid loss of color information, such as the tint or hue of an image recreated from the processed signal. Preferably, the phase of the processing operation should be within 2.degree. of the chrominance signal.
To maintain a precise phase relationship between the transmitted chrominance signal and a chrominance signal processing operation, a color synchronizing burst signal, shown in FIG. 1A, is transmitted with the chrominance signal to provide a phase reference for the processing operation. The color synchronizing burst is a short, unmodulated signal usually consisting of nine cycles and is located on the back-porch of the horizontal blanking interval, after the horizontal sync pulses.
A chrominance processing operation uses the color synchronizing burst to generate an internal reference signal. The reference signal is generated by an Automatic Phase Control (APC) operation which separates and amplifies the color synchronizing burst signal, and then locks the phase of a local reference oscillator of the same frequency as the burst signal to the phase of burst signal.
In analog chrominance signal processing, the phase-locking is usually provided by a phase locked-loop, as shown in FIG. 2, or a phase controlled oscillator. Typically, the phase-locked loop is formed by a DC voltage controlled oscillator (VCO) 40, which generates the internal reference signal, in combination with a phase detector 42 and a low pass filter 41. The phase detector 42 is supplied with the VCO output signal and the color synchronizing burst signal and generates a DC output having polarity and amplitude proportional to the direction and magnitude of the relative phase difference between the VCO output signal and the color synchronizing burst signal. The DC output is filtered by the low pass filter 41 and supplied to the VCO 42 to control the phase of the oscillator output signal. The DC output is varied until the phase of the oscillator output signal matches the phase of the color synchronizing burst signal. The low pass filter 41 modifies the dynamic performance of the phase locked loop by changing the DC loop gain.
To achieve proper balance between the color and the luminance amplitudes, and thus avoid oversaturation of bright colors in a reproduced image, the gain of the chrominance signal must be maintained at a constant level to compensate for changes in the chrominance signal caused by variations in scenes, transmission, propagation and receiver fine tuning. Typically, the color and the luminance amplitudes are balanced by an Automatic Chroma Control (ACC) operation provided by a feedback system which detects the amplitude of the color synchronizing burst signal and supplies a DC voltage to an amplifier to maintain the burst signal at a constant level and thus prevent the maximum amplitude of the chrominance signal from exceeding a predetermined value.
Similarly, in digital chrominance signal processing, APC and ACC operations are necessary. As an example, FIG. 3 illustrates a known circuit for processing a digitized composite video signal to generate primary color signals. The circuit includes a Y/C separating circuit 20, a video processing circuit 21, an automatic chroma control (ACC) circuit 23, an automatic phase control (APC) circuit 24, a color signal demodulator 25, and a matrix circuit 22.
The Y/C separating circuit 20 separates the composite digital video signal into a portion representing a digitized luminance signal (Y signal) and a portion representing a digitized chrominance signal (C signal). The Y/C separating circuit 20 delivers the Y signal to the video processing circuit 21 which functions to amplify the Y signal, perform additional processing operations and deliver the processed Y signal to matrix circuit 22.
The Y/C separating circuit 20 also delivers the C signal to the ACC circuit 23 which operates to balance the amplitude of the C signal to provide a constant level C signal. The ACC circuit delivers the constant level C signal to the automatic phase control (APC) circuit 24 and to the color signal demodulator circuit 25.
The APC circuit 24 responds to a burst gate pulse signal to process the constant level C signal to generate a reference clock signal f.sub.sc having a phase locked to the color synchronizing burst signal. The APC circuit 24 also generates a sampling clock signal of frequency 4f.sub.sc. The APC circuit 24 delivers the sampling clock signal 4f.sub.sc to the color signal demodulator circuit 25 which uses the sampling clock signal as an internal reference clock for demodulating the constant level C signal delivered by ACC circuit 23. The color signal demodulator circuit 25 recovers color difference signals R-Y, G-Y and B-Y by sampling the C signal under the timing of the sampling clock signal 4f.sub.sc and delivers the color difference signals to matrix circuit 22 which linearly cross-mixes the color difference signals R-Y, G-Y and B-Y with the Y signal in predetermined proportions to produce primary color signals R, G and B.
FIG. 4 illustrates the APC circuit 24 shown in FIG. 3. Generally, the APC circuit 24 phase-locks the reference clock signal f.sub.sc to the phase of the color synchronizing burst signal in a manner analogous to the analog APC circuit shown in FIG. 2. As shown in FIG. 4, the APC circuit includes a phase comparator circuit 26, a lag/lead filter circuit 27, a digital-to-analog (D/A) converter circuit 28, a voltage controlled oscillator (VCO) circuit 29 and a frequency divider circuit 30 sequentially arranged to form a phase-locked loop.
The phase comparator circuit 26 is operative to separate the color synchronizing burst signal portion of the digitized chrominance signal using the burst gate pulse signal as a reference. The phase comparator circuit 26 compares the phase data derived from the color synchronizing burst signal portion of the C signal with the reference clock signal f.sub.sc and delivers a digital signal representing the direction and magnitude of the relative phase difference between the color synchronizing burst signal and the reference clock signal f.sub.sc to the lag/lead filter 27. The lag/lead filter 27 operates to modify the dynamic performance of the phase locked loop in a manner analogous to that of the low pass filter 41 of the analog circuit of FIG. 2, and the lag/lead filter 27 delivers filtered digital output to D/A converter 28. The filtered digital output is converted to an analog DC output by D/A converter 28 which delivers the DC output to the VCO 29. The VCO 29 generates a sampling clock signal 4f.sub.sc having a frequency four times that of the reference clock signal and having a phase controlled by the DC output and delivers the sampling clock signal to the frequency divider 30 to generate the reference clock signal f.sub.sc.
As in the analog APC circuit, the relative phase difference between the color synchronizing burst signal and the reference clock signal causes the VCO 29 to generate a sampling clock signal 4f.sub.sc of different phase such that the relative phase difference is smaller. The phase of the sampling clock signal is varied until the relative phase difference between the color synchronizing burst signal and the reference clock signal is eliminated. When the relative phase difference is eliminated, the phase of the sampling clock and reference clock signals remain constant, and the APC circuit is phase locked.
FIG. 5 illustrates the analog chrominance signal from which the digitized chrominance signal is generated and shows locations corresponding to those sampled by the color signal demodulator circuit 25. When the APC circuit 24 is properly phase locked, the APC circuit 24 delivers the sampling clock signal 4f.sub.sc to the color signal demodulator circuit 25 to time the chrominance signal sampling such that the chrominance signal is sampled at those locations whereat the color difference values B-Y and the color difference values R-Y are indicated. The phase locking of the APC circuit thus allows recovery of the B-Y and R-Y color difference signals in one sampling operation.
FIG. 6 illustrates the ACC circuit 23 shown in FIG. 3. Generally, the ACC circuit operates in a manner analogous to the ACC circuit used in processing analog chrominance signals and prevents the maximum amplitude represented by the digital chrominance signal from exceeding a predetermined value. As shown in FIG. 6, the ACC circuit includes, in sequence, a multiplier circuit 31, a burst peak detector circuit 32, a comparator circuit 33 and an integrator circuit 34 arranged to form a feedback loop.
The multiplier 31 is operative to deliver the digitized chrominance signal to burst detector 32 which detects the maximum amplitude of the color synchronizing burst signal and supplies the detected maximum amplitude to the comparator circuit 33. The comparator circuit 33 compares the detected maximum amplitude to a reference level and forms a difference signal representing the difference between the detected maximum amplitude and the reference level. The comparator circuit 33 delivers the difference signal to the integrator circuit 34 which integrates the difference signal over a time period, such as over one horizontal line period, to calculate coefficient data which correspond to the difference between the detected maximum amplitude and the reference level. The integrator circuit 34 supplies the coefficient data to multiplier circuit 31 which multiplies each component of the chrominance signal by a portion of the coefficient data to modify the amplitude of the C signal and generate a digital chrominance signal having a constant level. The multiplier 31 delivers the constant level chrominance signal to the APC circuit 24 for phase locking and to the demodulator circuit 25 for separation of the color difference signals, as well as to the burst peak detector 32 for further level balancing.
As shown in FIG. 3, the known digital chrominance signal processing circuit has the drawback that the circuit elements are dedicated to only one operation. The APC circuit elements are used only for the APC operation and are not available for other signal processing operations, such as for the ACC operation, though the two operations have overlapping functions. Likewise, the ACC circuit elements are available only for the ACC operation and are not available for other signal processing operations, such as the APC operation. Because the circuit elements are dedicated to only one operation, the number of circuit elements used in the signal processing circuit is greatly increased and the size of the circuit is likewise increased. Furthermore, because separate circuit elements are used to perform overlapping functions in several operations, the circuit elements are used inefficiently.